The processors or microprocessors presently in use perform their operations in compliance with the instructions of a control program (or code) which is generally to be found in non-volatile memory of the ROM type. The control program is "masked", i.e. it is made during manufacture of the integrated circuit by the masking technique.
Because of errors in certain instructions of the control program in non-volatile memory, or because the control program needs to be modified, it can happen that it is desired to perform one or more patches, each consisting in replacing the erroneous instruction or sequence of instructions or modified instructions by a replacement routine which is known as a "patch".
If the control program were stored in read/write memory or RAM, or indeed in electrically programmable read-only memory (EPROM), then actual replacement would indeed be possible. However, in the present case, because the control program is in (masked) non-volatile memory, such actual replacement is not possible.
Conventionally, a control program stored in ROM is patched by diverting the control program while it is running to a corrected or modified patch stored in RAM and generally located outside the chip on which the processor and the ROM are formed.
In a known technique, branching instructions are inserted at regular intervals in the control program. Executing each branching instruction amounts to diverting (first jump) the execution of the control program to an address which is situated in RAM and which contains a jump instruction (second jump):
either to the address of a patch routine, supposing that certain instructions in the control program following the branching instruction include errors or need to be modified;
or else, in the absence of errors, to a return address in the control program immediately following the address of the branching instruction.
In other words, the address of each branching instruction constitutes a predefined trap address and corresponds necessarily to two jumps.
That known technique suffers from several drawbacks. Firstly, it increases the real time constraints on the control program since two jumps need to be executed at each trap address, whether or not there is a patch to be performed. In addition, it requires RAM of large size if it is desired to make a large number of trap addresses available within the control program, because each patch stored in RAM contains not only corrected or modified instructions but also a copy of the entire program segment situated between the trap address concerned and the address of the instructions that are to be corrected or modified.
In order to mitigate the drawbacks of that known technique, control program patching apparatus has been proposed comprising, in particular:
means for storing a plurality of trap addresses, each associated with the address of one of the patch routines;
a means for comparing the address of the control program contained in the program counter with each of the trap addresses contained in the storage means; and
means for diverting the control program if the comparator means deliver a positive comparison, with diversion being to a patch routine whose address is associated with the trap address concerned by the positive comparison.
That known apparatus operates as follows: on each instruction cycle, it is determined whether the instruction being executed is one of the trap addresses, and on detecting a match, the logic of the apparatus changes the current address in the program counter, replacing it with the address of the patch routine.
That known apparatus presents several advantages over the above-mentioned known technique. In particular, it makes it possible to provide a patch at any address in the control program (since it is possible to select which addresses are stored as trap addresses in the storage means), while minimizing the size of the RAM required for the patches (since the patch routines contain only those instructions that have been corrected or modified, and is the means for storing the trap addresses take up little memory space).
However, as presently designed, that known apparatus does not deliver performance that is as good as desired since it makes it possible to provide only a limited number of corrections to the control program.
In order to guarantee the operating speed of the processor and restrict the area of silicon required, the number of trap addresses with which the comparator means can compare the address contained in the program counter must necessarily be limited.
Thus, at present, only a small number of correction opportunities are available (e.g. eight). In other words, only a few patch routines can be used with a given control program. Unfortunately, it often happens that it is desirable to provide a larger number of corrections or modifications to the control program.